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RV32I Out-of-Order CPU Simulato

2026-04-01T00:00:00.000Z [in-progress]
systems , C / C++
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  • Built a cycle-accurate RV32I out-of-order CPU simulator in C++17, modeling fetch, decode, rename,

issue, execute, and in-order commit with ROB, issue queue, and physical register renaming.

  • Implemented configurable microarchitecture components including ALU/load-store/branch units,

gshare/bimodal branch predictor, BTB, and L1/L2 cache hierarchy with LRU/PLRU replacement

policies.

  • Added bare-metal RV32I ELF workload support, JSON-based simulator configuration, detailed

per-instruction and aggregate performance statistics, and unit tests for pipeline, cache, predictor, ROB, and